? semiconductor components industries, llc, 2013 january, 2013 ? rev. 1 1 publication order number: ncs36000/d ncs36000 passive infrared (pir) detector controller the ncs36000 is a fully integrated mixed ? signal cmos device designed for low ? cost passive infrared controlling applications. the device integrates two low ? noise amplifiers and a ldo regulator to drive the sensor. the output of the amplifiers goes to a window comparator that uses internal voltage references from the regulator. the digital control circuit processes the output from the window comparator and provides the output to the out and led pin. features ? 3.0 ? 5.75 v operation ? ? 40 to 85 c ? 14 pin soic package ? integrated 2 ? stage amplifier ? internal ldo to drive sensor ? internal oscillator with external rc ? single or dual pulse detection ? direct drive of led and out ? this is a pb ? free device typical applications ? automatic lighting (residential and commercial) ? automation of doors ? motion triggered events (animal photography) 6 vref ldo & voltage references amplifier circuit window comparator system oscillator digital control circuit 5 op1_p 4 op1_n 3 op1_o 2 op2_n 1 op2_o 7 vss 14 vdd 13 osc 2 2 8 out 9 led 10 xled_en 12 mode figure 1. simplified block diagram 14 soic ? 14 d suffix case 751a 1 see detailed ordering and shipping information in the package dimensions sect ion on page 7 of this data sheet. ordering information pin connections (top view) http://onsemi.com ncs36000g awlyww 1 14 a = assembly location wl = wafer lot y = year ww = work week g = pb ? free package marking diagrams 1 2 3 4 5 6 7 14 13 12 11 10 9 8 op2_o op2_n op1_o op1_n op1_p vref vss vdd osc mode nc xled_en led out
ncs36000 http://onsemi.com 2 pin function description pin no. pin name description 1 op2_p output of second amplifier 2 op2_n inverting input of second amplifier 3 op1_o output of first amplifier 4 op1_n inverting input of first amplifier 5 op1_p non ? inverting input of first amplifier 6 vref regulated voltage reference to drive sensor 7 vss analog ground reference. 8 out cmos output (10 ma max) 9 led cmos output to drive led (10ma max) 10 xled_en active low led enable input 11 nc no connect 12 mode pin used to select pulse count mode 13 osc external oscillator to control clock frequency 14 vdd analog power supply absolute maximum ratings rating symbol value unit input voltage range (note 1) v in ? 0.3 to 6.0 v output voltage range v out ? 0.3 to 6.0 v or (v in + 0.3), whichever is lower v maximum junction temperature t j(max) 140 c storage temperature range t stg ? 65 to 150 c esd capability, human body model (note 2) esd hbm 2 kv esd capability, machine model (note 2) esd mm 200 v lead temperature soldering reflow (smd styles only), pb ? free versions (note 3) t sld 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. refer to electrical characteristics and application information for safe operating area. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec ? q100 ? 002 (eia/jesd22 ? a114) esd machine model tested per aec ? q100 ? 003 (eia/jesd22 ? a115) latchup current maximum rating: 150 ma per jedec standard: jesd78 3. for information, please refer to our soldering and mounting techniques reference manual, solderrm/d thermal characteristics rating symbol value unit thermal characteristics, dfn6, 3x3.3 mm (note 4) thermal resistance, junction ? to ? air (note 5) thermal reference, junction ? to ? lead2 (note 5) r ja r jl will be completed once package and power consumption is finalized c/w thermal characteristics, tsop ? 5 (note 4) thermal resistance, junction ? to ? air (note 5) r ja see note above. c/w 4. refer to electrical characteristics and application information for safe operating area. 5. values based on copper area of 645 mm 2 (or 1 in 2 ) of 1 oz copper thickness and fr4 pcb substrate .
ncs36000 http://onsemi.com 3 operating ranges (note 6) rating symbol min typ max unit analog power supply v dd 3.0 5.0 5.75 v analog ground reference v ss 0.0 0.1 v supply current (standby, no loads) i dd 170 a digital inputs (mode) v ih 0.7 * v dd v dd v dd + 0.3 v v il vss v dd * 0.28 digital output (out, led) push ? pull output (10 ma load) v oh 0.67 * v dd v dd v v ol vss v dd * 0.3 op1_p (sensor input) (note 7) amp 1 in 0.1 v dd ? 1.1 v ambient temperature t a ? 40 85 c 6. refer to electrical characteristics and application information for safe operating area. 7. guaranteed by design (non ? tested parameter). electrical characteristics v in = 1 v, c in = 100 nf, c out = 100 nf, for typical values t a = 25 c; unless otherwise noted. parameter test conditions symbol min typ max unit ldo voltage reference output voltage v dd = 3.0 v to 5.75 v vref 2.6 2.7 2.8 v supply current v dd = 3.0 v to 5.75v iref 20 50 a comparator high trip level v h 2.413 2.5 2.588 v comparator low trip level v l 1.641 1.7 1.760 v reference voltage for non ? inverting input of second amplifier v m 2.007 2.1 2.174 v system oscillator oscillator frequency v dd = 5.0 v r 3 = 220 k c 2 = 100 nf osc 62.5 hz window comparator lower trip threshold see vl above higher trip threshold see vh above differential amplifiers (amplifier circuit) dc gain v dd = 5.0 v (note 8) av 80 db common ? mode input range v dd = 5.0 v (note 8) cmir 0.1 v dd ? 1.1 v power supply rejection ratio v dd = 5.0 v (note 8) psrr 60 db output drive current v dd = 5.0 v (note 8) i out1 25 a por por release voltage v por 1.35 2.85 v 8. guaranteed by design (non ? tested parameter).
ncs36000 http://onsemi.com 4 applications information oscillator the oscillator uses an external resistor and capacitor to set the system clock frequency. multiple clock frequencies can be selected using different combinations of resistors and capacitors. figure 2 shows a simplifier block diagram for the system oscillator. + ? + ? osc 13 q q set clr s r 14 vdd figure 2. block diagram of system oscillator circuit ldo regulator the ldo regulator provides the reference voltage for the sensor and all other analog blocks within the system. the nominal voltage reference for the sensor is 2.7 v 5%. an external capacitor is needed on the vref pin to guarantee stability of the regulator. differential amplifiers the two differential amplifiers can be configured as a bandpass filter to condition the pir sensor signal for the post digital signal processing. the cutoff frequencies and passband gain are set by the external components. see figure 5. 10 ? 1 10 0 10 1 20 30 40 50 60 70 80 figure 3. plot showing typical magnitude response of differential amplifiers when configured as a bandpass filter window comparator the window comparator compares the voltage from the second differential amplifier to two reference voltages from the ldo regulator. comp_p triggers if op2_o is greater than the vh voltage and comp_n triggers if op2_o is lower than the vl voltage. see figures 4 and 5. vh vl vdd vss comp_p vdd vss comp_n op2_o vm figure 4. plot showing functionality of window comparator for an analog input op2_o
ncs36000 http://onsemi.com 5 4 + ? 5 3 + ? 2 1 g d vref ldo 6 sensor dependent components vm vref 6 vm vh vl application dependent components + ? vl vh op2_o + ? comp_p comp_n figure 5. figure showing simplified block diagram of analog conditioning stages digital signal processing block (all times assume a 62.5 hz system oscillator frequency) the digital signaling processing block performs three major functions. the first function is that the device toggles led during the start ? up sequencing at approximately two hertz regardless of the state of the xled_en pin. the startup sequence lasts for thirty seconds. during that time the out pin is held low regardless of the state of op2_o. the second function of the digital signal processing block is to insure a certain glitch width is seen before out is toggled. the digital signal processing block is synchronous with the system oscillator frequency and therefore the deglitch time is related to when the comparators toggle within the oscillator period. a signal width less than two clock period is guaranteed to be deglitched as a zero. a signal width of greater than three clock cycles is guaranteed to be de ? glitched. it should be noted that down ? sampling can occur if sufficient anti ? aliasing is not performed at the input of the circuit (opi_p) or if noise is injected into the amplifiers, an example would be a noisy power supply. the third function of the digital signal processing block is to recognize different pulse signatures coming from the window comparator block. the device is equipped with two pulse recognition routines. single pulse mode (mode tied to vss) will trigger the out pin if either comparator toggles and the deglitch time is of the appropriate length. (see figure 6). dual pulse mode (mode tied to v dd ) requires two pulses with each pulse coming from the opposite comparator to occur within a timeout window of five seconds (see figure 7). if the adjacent pulses occur outside the timeout window then the digital processing block will restart the pulse recognition routine (figure 8). xled_en pin the xled_en pin enables the led output driver when motion has been detected. if xled_en is tied high the led pin will not toggle after motion is detected. if the xled_en is tied low the led pin will toggle when motion is detected. during start-up the led pin will toggle irrespective of how the xled_en pin is tied. (see figure 6). osc ??????????????????????? ??????????????????????? ?????? ?????? start ? up sequencing comp_p out comp_n <32m sec >48m sec >48m sec ~1.6 sec ~1.6 sec if xled_en = 0 if xled_en = 0 mode op2_o figure 6. timing diagram for single ? pulse mode detection
ncs36000 http://onsemi.com 6 osc ??????????????????????? ?????? ?????? start ? up sequencing comp_p out comp_n <32m sec >48m sec >48m sec ~1.6 sec if xled_en = 0 mode op2_o >48m sec < 5 sec ??????? ??????? timeout counter figure 7. timing diagram for dual ? pulse mode detection osc ??????????????????????? ?????? start ? up sequencing comp_p out comp_n <32m sec >48m sec >48m sec mode op2_o > 5 sec ????? ????? timeout counter 5 sec ?????? ?????? figure 8. timing diagram for two pulses outside timeout window
ncs36000 http://onsemi.com 7 led out op2_o op2_n op1_o op1_n op1_p vref vss xled_en nc vdd osc mode 1 2 3 4 5 6 7 14 13 12 11 10 9 8 g d sensor dependent components power supply / ac to dc rectifier r1 r2 r3 r4 c1 c2 c3 c4 c6 c5 r5 d1 r7 c7 j1 j2 r6 microcontroller figure 9. typical application diagram using ncs36000 r1 = 10 k c1 = 33 f j1 (jumper for xled_en) r2 = 560 k c2 = 10 nf j2 (jumper for mode select) r3 = 10 k c3 = 33 f d1 (led) r4 = 560 k c4 = 10 nf r5 = 43 k c5 = 100 nf r6 = 1 k c6 = 100 nf r7 = 220 k c7 = 100 nf 9. r1, c1, r2, c2, r3, c3, r4, c4 setup bandpass filter characteristics. with components as shown above the passband gain is app roximately 70 db with the 3 db cutoff frequency of the filter at approximately 700 mhz and 20 hz. 10. r4 can be replaced by a potentiometer to adjust sensitivity of system. note dynamically changing r4 will also change the pol e location for the second amplifier. 11. r5 and c5 are sensor dependant components and r6 may need to be adjusted to guarantee the amp 1 in parameter outlined within the operating ranges section of this document. 12. r7 and c7 may be adjusted to change the oscillator frequency. r7 may not be smaller than 50 k . ordering information device package shipping ? NCS36000DG soic ? 14 (pb ? free) 55 units / rail ncs36000drg soic ? 14 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncs36000 http://onsemi.com 8 package dimensions soic ? 14 d suffix case 751a ? 03 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 7.04 14x 0.58 14x 1.52 1.27 dimensions: millimeters 1 pitch 7x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademar ks of semiconductor components industries, llc (s cillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to an y products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of th e application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products ar e not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associ ated with such unintended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action em ployer. this literature is subject to all applicable copyrig ht laws and is not fo r resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncs36000/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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